The present disclosure relates to a semiconductor structure, and particularly to a dynamic random access memory (DRAM) cell including word lines located in two levels and a method of manufacturing the same.
Deep trench capacitors are used in a variety of semiconductor chips for high areal capacitance and low device leakage. Typically, a deep trench capacitor provides a capacitance in the range from 4 fF (femto-Farad) to 120 fF. A deep trench capacitor may be employed as a charge storage unit in a dynamic random access memory (DRAM), which may be provided as a stand-alone semiconductor chip, or may be embedded in a system-on-chip (SoC) semiconductor chip. A deep trench capacitor may also be employed in a variety of circuit applications such as a charge pump or a capacitive analog component in a radio-frequency (RF) circuit.
A strap structure is employed to provide an electrically conductive path between an inner electrode of a deep trench capacitor and the source of an access transistor. As dimensions of semiconductor devices scale, dimensions available for forming deep trench capacitors and strap structures continue to shrink.